Advancement in Phase Locked Dielectric Resonator Oscillators | Loan-Finance

Advancement in Phase Locked Dielectric Resonator Oscillators

POSTED BY admin on Nov 19, 2008 under Business

Phase
Locked Dielectric Resonator Oscillators (PDROs) are widely used in
both commercial and military applications PDROs offer low cost,
small size, low noise, efficient power consumption and high
reliability required for local oscillator generation in commercial
applications such as modern radar, communication, and test
instrumentation systems PDROs offers lower phase noise, lower
spurious, smaller size, millimeter wave frequencies of operation, and
higher output power options

Phase
Locked Dielectric Resonator Oscillators (PDROs) are widely used in
both commercial and military applications. PDROs offer low cost,
small size, low noise, efficient power consumption and high
reliability required for local oscillator generation in commercial
applications such as modern radar, communication, and test
instrumentation systems. PDROs offers lower phase noise, lower
spurious, smaller size, millimeter wave frequencies of operation, and
higher output power options.

The
standard PDRO consists of a BJT or GaAs MESFET fundamental Voltage
Tuned Dielectric Resonator Oscillator (VTDRO) which is phase locked
via a sampling loop to a low noise crystal oscillator reference. The
phase locked loop (PLL) acts as a low pass filter to the multiplied
up reference phase noise and as a high pass filter to the VTDRO’s
phase noise.

In order to take
advantage of these low noise references, the PLL noise floor of the
PDRO needs to be equally low. If the noise floor of the PLL is not
low enough, the noise floor of the PLL will limit the noise inside
the loop. Digital loops with 100 MHz phase detector frequencies have
a limited noise floor of around -150 dBc/Hz. In contrast, the
sampling phase locked loop in the PDRO exhibits a typical phase noise
floor of -162 dBc/Hz with a 100 MHz phase detector frequency. Equally
important to the performance of a sampling PLL is the design of the
reference amplifier. The reference amplifier on the input of the PLL
must not degrade the reference phase noise. This amplifier must also
maintain a constant signal level to the phase detector over
variations in temperature from -45 to +85ºC along with reference
level variations of +/- 5dB.

Through
the use of proprietary sampling phase locked loop circuitry, single
loop PDRO models provide exceptionally low phase noise, typically
-120 dBc at 10 kHz offset from a 13 GHz carrier when phase locked to
an external 100 MHz crystal reference. This proprietary low loop
phase noise floor, along with the inherent low phase noise of the
VTDRO, allows the use of wide loop bandwidths of approximately 200kHz
to 300kHz. Wide loop bandwidths enable low microphonics and phase hit
free operation , two critical parameters in both commercial and
military systems.

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